PhD School Speakers’ Team and Abstracts

Abstract

For over 20 years, SiGe heterojunction bipolar transistors (HBTs) have shown their competitiveness for millimeter-wave circuits, now with operating frequencies well beyond 100 GHz. Besides excellent radio-frequency performance, customer focus is also particularly put on operating constraints (Safe Operating Area) and long-term reliability of the devices. The main reliability issue in SiGe HBTs is the cumulative base current degradation they may experience during circuit operation. This continuous transistor aging is the result of the interplay between trap creation and annihilation caused by hot-carrier injection. Based on extensive electrical stress tests, HBT aging functions can be derived to model device degradation and enable 10-year lifetime extrapolations.

Gerhard G. Fischer studied Physics at the University of Würzburg, Germany. From 1993 to 1997 he was with IHP Frankfurt (Oder) as research associate, investigating epitaxial SiGe layers by X-ray diffraction and received his Ph.D. in Physics from University of Potsdam in 1997. Afterward, he worked as post-doc at the Metallurgical Department of the University Clausthal-Zellerfeld, Germany. In 1999 he joint again IHP Frankfurt, where he was engaged in CMOS technology transfers from Motorola and Intel supervising IHP’s in-line (cleanroom) metrology. From 2006 on, he became responsible for developing and maintaining SiGe HBT compact models. In connection with the BMBF project “KOKON” where automotive SiGe HBT radar sensors were being developed, he started his occupation with SiGe HBT reliability issues. Currently, he is also in the process of taking over IHP BiCMOS technology qualification and reliability responsibilities. Besides these activities, he found time to publish around 20 papers for international journals  and conferences.

Abstract

High voltages in semiconductors can lead to the occurrence of charge carriers with energies high enough to damage the interfaces between the semiconductors and insulators, giving rise to degradation of the device characteristics over time (aging). Detailed simulation of these so-called hot carriers based on a microscopic transport model reveals the device internal processes, which are not directly accessible by measurements. It is shown that, under important stress conditions, hot holes generated by impact ionization of hot electrons are responsible for the degradation of SiGe HBTs and silicon power MOSFETs. With these albeit very CPU intensive and complicated models it is even possible to obtain reasonable quantitative agreement between measurement and simulation.

Christoph Jungemann received the Dipl.-Ing. degree (M.Sc.) and the Dr.-Ing. degree (Ph.D.) in Electrical Engineering from RWTH Aachen University in 1990 and 1995, respectively. After positions in the R&D department of Fujitsu in Japan, University of Bremen, Stanford University, Technical University of Braunschweig, Bundeswehr University in Munich, he became a Full Professor at RWTH Aachen University for electromagnetic theory in 2011. His research focuses on semi-classical transport in semiconductor devices including AC and noise analyses. Currently he works on microscopic transport in SiGe HBTs, MOSFETs, power devices, OLEDs, ReRAM and THz devices.

He has published two books and two book chapters on transport modeling, 85 articles in international journals, and about 200 papers at peer-reviewed conferences. He was an editor of the IEEE Transactions on Electron Devices from 2007 until 2010. In 2006 he received the IEEE Paul-Rappaport-Award.

Abstract

In the last three decades several approaches have been proposed for the construction of compact thermal models (CTMs) of electronics components and packaging. In this talk, the Author will address a set of novel model-order reduction techniques he has recently proposed, suited to extract CTMs from detailed models of heat conduction problems, with unprecedented degrees of efficiency and accuracy.

Various approaches will be presented for different classes of CTMs, including dynamic CTMs, boundary-condition independent CTMs, parametric CTMs with both material and geometrical parameters, nonlinear CTMs including thermal properties varying with temperatures. It will be shown how such techniques allow an ultra-fast extraction of CTMs, ensuring very high levels of accuracy with respect to the detailed models of very complex geometries with several millions of degrees of freedom.

Lorenzo Codecasa received the M.Sc. degree and the Ph.D. degrees, both in Electronics Engineering, from Politecnico di Milano, in 1997 and 2001, respectively. From 2002 to 2010 he worked as Assistant Professor of Electrical Engineering with the Department of Electronics, Information, and Bioengineering of Politecnico di Milano. Since 2010 he has worked as Associate Professor of Electrical Engineering in the same Department. His main research contributions are in theoretical analysis and computational investigation of electric circuits and electromagnetic fields. He is also particularly active in the research of heat transfer and thermal management of electronic devices and systems, in which he has introduced original approaches to the extraction of compact thermal models, aimed at the efficient thermal simulation of packages and electrothermal simulation of electronic circuits. He has authored or coauthored over 170 papers in refereed international journals and conference proceedings. In 2016 he received the Harvey Rosten Award for Excellence. He is currently serving as Associate Editor for the IEEE Transactions of Components, Packaging and Manufacturing Technology. He is also member of the Steering Committee and future General Chair of the THERMINIC conference.

Abstract

Photovoltaic (PV) systems may suffer from a number of malfunctions or faults affecting the PV cells, modules, connections, power electronics, control algorithms among others. In this talk, a general overview of the main issues is given and a more in-depth discussion of the reliability problems related to the PV generator, power electronics and control is provided. Effects of aging, environmental factors and shadowing on the performance of PV cells and modules are discussed. Reliability aspects concerning the PV power processing systems, especially power electronics converters and control algorithms (e.g., Maximum Power Point Tracking), which are implemented through them, are overviewed. Results from current literature and also referring to commercial products are presented to the aim of giving hints and suggestions for stimulating students’ research activity in the field. The lecture does not require an advanced knowledge on PV systems.

Giovanni Spagnuolo received the M.Sc. degree in Electronics Engineering from the University of Salerno and the Ph.D. degree in Electrical Engineering from the University Federico II of Naples in 1993 and 1998, respectively. Since January 2016 he is IEEE Fellow “for contributions to control of photovoltaic systems” and since May 2016 he is Full Professor of Electrical Engineering at the University of Salerno. He was in the 2015 Thomson Reuters list of Most Influential Minds. From 2012 to 2014 he chaired the Technical Committee on Renewable Energy Systems of the IEEE Industrial Electronics Society. Since January 2011 he has been serving as Member of the Steering Committee and Editor for the topic “PV system control” of the IEEE Journal of Photovoltaics. Since January 2007 he has been serving as associate editor of the IEEE Transactions on Industrial Electronics. He is co-author of five international patents, of two books and of about 70 papers published in international journals.

Abstract

The term Failure Analysis (FA) indicates the process of analyzing a failed electron device to determine the cause of the failure. This procedure starts from the observation of the failure mode to discover the failure mechanism, and is suited to provide information useful for technology advancement and corrective actions necessary to fix the problem. The role of FA in the assessment of reliability is widely acknowledged, and the best-known failure mechanisms have obtained the introduction of process steps in manufacturing microelectronics that are dedicated to their prevention. In this talk, FA logic and rules will be explained in terms of good and bad practices. Special emphasis will be placed on case studies of optoelectronic devices.

Biography

Giovanna Mura received the M.Sc. degree in Electronics Engineering and the Ph.D. degree in Electronics Engineering and Computer Science in 2000 and 2004, respectively, both from University of Cagliari. Since 2012 she is Assistant Professor in the Department of Electric and Electronic Engineering of the same University. She has been teaching courses on the reliability and diagnostics of electron devices in the M.Sc. course in Electronics Engineering. Her research activities have been mainly focused on failure physics in solid-state electronics, technological characterization by electron microscopy (SEM and TEM), failure analysis of electron and photonics devices, and general methods for reliability assessment with special focus on life-testing and quality insurance protocols. She is author of more than 60 papers published on international journals or presented at international conferences.

Abstract

Part I: The evolution of power semiconductor modules is characterized by increasing levels of structural and functional integration. Moreover, growing and upcoming applications demand more and more the ability to operate in harsh environments, at the same time requesting improved robustness, reliability and availability. This stimulates novel built-in reliability design approaches and health monitoring methodologies. This talk will review some fundamentals aspects of power module degradation and failure, and present some advanced power module design and assembly options.

Part II: The ability to assess the health status of power modules during their operation is key to meet increasingly tight performance and lifetime requirements of a number of pivotal electrical energy conversion applications of modern society. Indeed, that is a requirement for the implementation of preventive maintenance, which aims at anticipating the occurrence of failures and intervening on the system before any forced down-time is generated. This talk will review concepts and approaches enabling realistic on-board health monitoring and present proof-of-concept demonstration of an original solution, for the specific case of inverters used in railway traction.

Biography

Alberto Castellazzi is an Associate Professor of Power Electronics with The University of Nottingham, Nottingham, U.K. He has been active in power electronics research and development for about 20 years and has had extensive collaborations with major European and international industrial research laboratories and groups on publicly and privately funded research projects. He has authored or co-authored over 180 papers published in peer-reviewed specialist journals and conference proceedings, for which he also regularly acts as a reviewer. His main research interests are the enabling technologies of power electronics conversion, including characterization, modeling, application, packaging and cooling of power devices. Dr. Castellazzi is a member of the Technical Programme Committee of the ISPSD and ESTC conferences.

Abstract

Reliability represents a major bottleneck in the continuous downscaling of CMOS technologies. Although in nanoscale devices the number of defects decreases, their impact on the device performance increases. This talk reviews the basic theory of reliability and some of its more common applications to modern CMOS nanodevices. This talk will discuss the different phases of the reliability testing procedure: experiment definition, measurements, distribution fitting and extrapolation. It will be explained how this methodology is applied to three on-chip failure mechanisms: time-dependent dielectric breakdown (TDDB), bias temperature instability (BTI), and channel hot carrier (CHC). In particular, we will point out how some reliability issues must be reconsidered when the device scale enters the nanometer range.

Biography

Felice Crupi received the M.Sc. degree in Electronics Engineering from the University of Messina in 1997 and the Ph.D. degree in Engineering of the Electronic Systems from the University of Firenze in 2001. He is Associate Professor with the Department of Computer Engineering, Modeling, Electronics and Systems Engineering, University of Calabria. Since 2015, he is the Coordinator of Ph.D. in ICT at the University of Calabria. His primary research interests include electronic device reliability, design of ultra-low power analog circuits, early assessment of emerging technologies for logic and memory applications, design of low frequency noise instrumentation, and design of high-efficiency solar cells. He has co-authored about 200 papers published in peer-reviewed journals and international conferences. He served as a Technical Program Committee Member of the International Electron Devices Meeting and the International Reliability Physics Symposium. He is Associate Editor of the IEEE Transactions on Device and Materials Reliability.

Abstract

The continuous evolution of microelectronic technology allows a continuous increase of system complexity and performance, thus offering new opportunities for implementation and realization that were unthinkable a few years ago. However, such improvements come together with an increased vulnerability to failure conditions occurring in the field, which pose new challenges to reliability of circuits and systems. Environmental and operating conditions possibly compromising reliability in VLSI circuits and systems, as well as possible approaches to cope with them, will be described in the talk.

Biography

Cecilia Metra is the 2018 President-Elect and 2019 President of the IEEE Computer Society (CS). She is an IEEE Fellow, IEEE CS Golden Core Member, and a member of the IEEE Honor Society IEEE-HKN.

She is Full Professor at the University of Bologna, Italy, where she has worked since 1991, and from which she received a Ph.D. in Electronics Engineering and Computer Science. In 2002, she was visiting faculty consultant for Intel Corporation.

She has been a member of the Board of Governors of the IEEE Computer Society since 2013, and of the IEEE Council on Electronic Design Automation since 2015.

She is the Editor in Chief of the IEEE Transactions on Emerging Topics in Computing (2018-2020) and she was Editor in Chief of Computing Now (2013-2016) and Associate Editor in Chief of IEEE Transactions on Computers (2007-2012). She is on the IEEE Institute Advisory Board, as well as on editorial boards of several international journals.

She contributed to numerous IEEE international conferences/symposia/workshops as General/Program Chair/co-Chair (14 times), Vice-General/Program Chair/co-Chair (6 times), Topic/Track Chair (34 times), and Technical Program Committee member (94 times).

She has published extensively on design for test and reliability of integrated circuits and systems. Her research has received public and private funding (from companies such as Intel Corporation, STMicroelectronics, Alstom Transport, etc.) at national and international levels.

Abstract

The reliability of modern electron devices is strongly affected by the microscopic properties of novel materials. A novel simulation methodology relying on a multiscale modeling platform connecting the microscopic material properties to the device reliability is required, which allows self-consistently modeling charge transport and the material structural modifications occurring during device operations in various conditions. The physical description of the defect creation and the charge trapping allows simulating SILC, BTI, RTN and BD (TDDB) including statistics. Techniques for mapping the defect distribution from the interpretation of electrical measurements are presented. Results address on novel logic devices (e.g. III-V FET), innovative memories (e.g. RRAM, Fe-memories) and 2D materials.

Biography

Luca Larcher received the M.Sc. degree in Electronics Engineering from University of Padova in 1998, and the Ph.D. degree in Information Engineering from University of Modena and Reggio Emilia in 2002, where is Full Professor of Electronics. His main research field covers the modeling and characterization of both non-volatile memory devices and reliability mechanism affecting modern electron devices, with a focus on physical mechanisms governing the charge transport and degradation of novel electronic materials. He has worked on Flash memory devices, and innovative NVM technologies such as charge trapping memory devices, PCM, resistive-RAM, ferroelectric devices and selectors. He is also active in field of the characterization and design of integrated circuits for both communications and energy harvesting applications in CMOS technology. He co-authored a book, and more than 200 technical papers published on international journals and proceedings of international conferences.

Abstract

Uncertainty quantification (UQ) is fundamental for the successful design of high-speed electronic circuits. Monte Carlo is a well-known UQ approach. It is easy to implement but computationally expensive due to a very large number of simulations needed to achieve accurate results.

During this talk, novel techniques for efficient time-domain UQ of circuits described by large systems of equations will be presented. As part of the proposed algorithms, an efficient time-domain circuit simulation technique will be discussed, which is suited to compute the circuit time-domain response at different time instances independently. This makes time-domain simulations amenable to parallel computation, which is not possible with standard time-marching techniques commonly used for circuit simulation. Embarrassing parallelism can be achieved in both the stochastic space and the time-domain.

Biography

Francesco Ferranti received the B.S. degree in Electronics Engineering from University of Palermo, Italy, in 2005, the M.S. degree in Electronics Engineering from University of L’Aquila, Italy, in 2007, and the Ph.D. degree in Electrical Engineering from Ghent University, Belgium, in 2011. He is currently an Associate Professor at the Microwave Department at the Institut Mines-Télécom (IMT) Atlantique, Brest, France. His research interests include parameterized macromodeling and model-order reduction, sampling techniques, design space exploration, optimization, uncertainty quantification, multiphysics modeling, behavioral modeling, efficient design and characterization of complex systems. He has authored or co-authored 51 papers in international peer-reviewed journals, 50 papers in international peer-reviewed conferences, and 2 books chapters.

Abstract

Over the last few years, the research in the field of GaN-based power transistors has shown impressive advancements. Normally-off transistors with breakdown voltage higher than 1 kV have already been demonstrated, thus clearing the way for a massive penetration in the power conversion field. Despite the great potential of this technology, GaN-based transistors may still suffer from reliability issues. In this presentation, an overview is given on the most recent results in the field of GaN transistor reliability, by focusing on the following relevant aspects: (i) the degradation of normally-off transistors with P-type gate; (ii) the degradation of transistors under hard switching conditions; (iii) the degradation of the electrical characteristics of GaN-based vertical transistors submitted to gate- and drain-step stress, and the related trapping processes.

Biography

Gaudenzio Meneghesso received the M.Sc. degree in Electronics Engineering from the University of Padova in 1992, working on the failure mechanism induced by hot-electrons in MESFETs and HEMTs. In 1997, he received the Ph.D. degree in Electrical and Telecommunication Engineering from the University of Padova. Since 2011 is with University of Padova as Full Professor. His research interest involves mainly the electrical characterization, modeling, and reliability of several semiconductor devices: a) microwave and optoelectronics devices on III-V and III-N; b) RF-MEMS switches for reconfigurable antenna arrays; c) electrostatic discharge (ESD) protection structures for CMOS and SMART POWER integrated circuits including electromagnetic interference issues; d) organic semiconductor devices; e) photovoltaic solar cells based on various materials. Within these activities he published more than 800 technical papers (of which more than 100 invited papers and 10 best paper awards). He has been nominated to IEEE Fellow class 2013 with the following citation: “for contribution to the reliability physics of compound semiconductor devices”.